General Information

If you are interested in one of the topics but the type of thesis does not match, you can cantact the supervisor anyway. Maybe, the work can be adopted to your requirements or a similar topic can be found.

The Project Seminars listed here are only assigned to students who do not major in Computer Engineering (B.Sc. ETiT). Students who major in Computer Engineering have to do the Project Seminar in combination with the Bachelor Thesis and have therefore to be handled differently.

Open theses and research assistant jobs

Bachelor theses

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Modulimport in Rapidwright
C/C++ Java Software
Ansprechpartner: Jakob Wenzel,  Frühester Beginn: sofort
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Portierung der SpartanMC Benchmark Suite auf Vivado HLS
C/C++ Hardware Software Praktisch
Ansprechpartner: Johanna Rohde,  Frühester Beginn: sofort

Master theses

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Realisierung und Untersuchung von beliebigen Datenpfadbreiten in CGRAs
Java Verilog Hardware Software
Ansprechpartner: Dennis Wolf,  Frühester Beginn: sofort
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Implementierung einer Prefetch Engine für HLS
C/C++ Verilog Hardware Software
Ansprechpartner: Johanna Rohde,  Frühester Beginn: siehe Beschreibung
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Runtime Decoupling von Memory Dependencies
C/C++ Software Praktisch Englisch Deutsch
Ansprechpartner: Johanna Rohde,  Frühester Beginn: sofort

Project seminars bachelor

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Portierung der CHStone Benchmark Suite auf SpartanMC
C/C++ Software Praktisch
Ansprechpartner: Johanna Rohde,  Frühester Beginn: sofort

Project seminars master

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Implementierung eines Level-2 Caches
Verilog Hardware Praktisch
Ansprechpartner: Johanna Rohde,  Frühester Beginn: sofort
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Optimierung einer Unrolling Transformation mit Machine Learning
C/C++ Software
Ansprechpartner: Johanna Rohde,  Frühester Beginn: sofort

Research assistant jobs

  • Unfortunately there is nothing available in this category at the moment

Contact

Technische Universität Darmstadt

Department of Electrical Engineering and Information Technology

Computer Systems Group

Prof. Dr.-Ing. Christian Hochberger

Merckstr. 25

64283 Darmstadt

+49 6151 16-21150

+49 6151 16-21150

Key

Good knowledge in C required
Good knowledge in Java required
Good knowledge in Verilog required
Good knowledge in VHDL required
Hardware oriented thesis
Software oriented thesis
Practical thesis
Theoretical thesis
Report should be written in English
Report should be written in German
Additional HW/SW required
Demanding thesis
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